A wiring substrate couples electronic components such as semiconductor chips to a device. Electronic components have become highly integrated and highly sophisticated. Thus, there is a need to increase the density of wiring in wiring substrates. Japanese Laid-Open Patent Publication No. 2014-225632 describes one example of a wiring substrate that increases the wiring density. The wiring substrate described in the publication includes a core substrate, a first wiring layer formed on the core substrate, a first insulation layer covering the first wiring layer, a second wiring layer having a higher wiring density than the first wiring layer and formed on the first insulation layer, and a second insulation layer covering the first insulation layer and the second wiring layer.
Such a wiring substrate includes via holes that extend through the first insulation layer, which is located between the first wiring layer and the second wiring layer, from the first wiring layer to the second wiring layer. The via holes are filled with a via wiring layer that electrically connects the first wiring layer and the second wiring layer.
The step of forming the via holes includes laser processing performed on the first insulation layer and desmear processing performed on the first insulation layer after the laser processing is performed. The laser processing exposes a surface of the first wiring layer in the bottom of each via hole. The desmear processing removes residues of the first insulation layer from the exposed surface of the first wiring layer. The step of forming the via wiring layer includes a process for embedding a conductive material in the via holes and a process for polishing the conductive material. The embedding process fills the via holes with the conductive material and deposits the conductive material on the surface of the first insulation layer. The polishing process removes the deposited conductive material from the surface of the first insulation layer to form an end surface of the via wiring layer that is flush with the surface of the first insulation layer. Since the second wiring layer has a higher wiring density than the first wiring layer, the base layer for the second wiring layer needs to have a high level of flatness. The polishing process of the conductive material realizes such a high level of flatness.
The desmear processing roughens the surface of the first insulation layer. Thus, in the embedding process performed after the desmear processing, the conductive material is embedded in recesses that were formed in the surface of the first insulation layer when the desmear processing was performed. The conductive material remains in the recesses of the surface of the first insulation layer after the polishing process is performed on the conductive material. Consequently, the conductive material remaining in the recesses may short-circuit wirings in the second wiring layer formed on the surface of the first insulation layer. This hinders increases of the throughput yield.